1. Field of the Invention
The present invention generally relates to integrated circuit (IC) output pad driving circuitry and, more specifically, to a method and apparatus for a load adaptive pad driver for integrated circuits.
2. Description of the Related Art
Digital logic integrated circuits--also known as "die" and "chips"--such as microprocessors and memories, generate output signals as either a HIGH logic state, sometimes referred to as a "1," or a LOW logic state, sometimes referred to as a "0." Each logic state output signal is a predetermined, steady-state, signal level, for example, five volts DC for HIGH and zero volts for LOW. Typically, an IC output driver stage includes field effect transistors (FET) connected in series through a resistor to a selected IC output terminal, referred to as the "pad." This prior art is shown in FIG. 1. The logical signal to be output, "DATA," is applied to the gates of the FETs and, along with an OUTPUT ENABLE signal for the specified pad, drive the output pad. That is, it is the function of the output driver to switch the pad between data output signal levels. This basic output driver circuit is designed to have an output resistance of 10 to 100 ohms and to have driver FETs that are relatively small. In this case, this circuit is designed to drive a minimum load capacitance at or near to the design specification speed.
While the task seems simple enough, in state-of-the-art of integrated circuit fabrication technology where transistor gates are measured in a fraction of a micron, many factors affect operations, including the process used for fabrication (e.g., bipolar vs. CMOS, 0.5 micron vs. 0.35 micron, and the like), voltage and current loads, electrostatic discharge (ESD) surges, operating temperatures, load capacitance, and the like. When there is a current transition, di/dt, in a chip, electromagnetic inductive noise (EMI) is generated. When there are a large number of pads on the chip, there can be a large inductance in the chip's ground bus. When the signal on a number of pads switches state simultaneously, a large noise spike in the ground line occurs. Therefore, the system architecture designer must account for such contingencies in constructing output drivers.
For example, noise on chip pads is addressed by U.S. Pat. No. 5,039,874 (Anderson; assigned to the common assignee of the present invention) by selectively adding a second driver to increase signal transition speed on the output pad. Current surge problems are addressed by U.S. Pat. No. 4,825,099 (Barton) by using a controllably switched current mirror circuit. Prevention of load current peaks is addressed in EP 591750 (DE4233850) in which the pad is driven as a current controlled element during a first range of the output transistor output voltage and as a voltage controlled element during a second voltage range. However, none of these methodologies provide an active feedback with respect to determining whether output load conditions require auxiliary pad driving during an output pad signal transition between a HIGH and LOW data output signal level.
Therefore, there is a need for a load adaptive pad driver apparatus that will generate a substantially constant output signal transition speed at an IC output pad regardless of the load attached to any specific pad on the chip.